Baugh Wooley Multiplier Using Carry Save Addition for Enhanced PDP

Abstract

Multiplication represents one of the major functional blocks which determine the overall efficiency in the digital signal processing systems. This paper presents novel techniques to realize the Modified Baugh Wooley multiplier of depth five and the proposed methodology is verified and analyzed through comparison with existing counterpart structures. The array structure using ripple carry addition technique is implemented followed by use of carry save addition processes. The Power Delay Product (PDP) of the simple carry save implementation is found to be 6.3% lower than the ripple carry technique. When the partial products are computed in parallel using carry save addition, the power delay product reduces by 40% compared to the ripple carry technique.