Low Power Implementation of a RISC Machine Using Clock Gating Technique

Abstract

In this work, 8bit RISC stored program machine is designed for low power by making use of clock gating technique. RISC stored program machine consists of different components namely memory unit, processing unit and control unit and these components are modelled by using Verilog HDL. The different sub modules of the RISC stored program machine are the processing unit, control unit and memory unit. Thereafter, power analysis of each of the different modules is done separately and consumption of power is observed. Same calculation of consumption of power is repeated by applying latch free and latch based clock gating techniques to the modules and the power consumption after applying clock gating is observed. And reduction in the power consumption of modules with clock gating is observed as 45% while analyzing using the Xpower tool of Xilinx ISE.