Optimized Voter Circuit for Fault Tolerant Implementation in TMR

Abstract

Due to scaling down of devices, circuits are vulnerable to manufacturing faults, radiation interference and various other faults. This may result in malfunctioning of circuits due to the occurrence of such faults. So performance, reliability, power and area have now become even more critical factors to look into. Due to degradation of components over time and noise in general, the overall design may be affected and produce incorrect results. Hence, fault tolerant design is now very critical in electronics circuit design. In space applications, Single Event Upsets (SEU) can occur, which can lead to system failure. To mitigate such errors, TMR (Triple Modular Redundancy) technique can be used. Simulations and analysis were performed on Cadence Virtuoso ADE and RTL compiler. In this paper, we present our fault tolerant voter circuit which might tolerate a fault and provide error free output by masking the fault which may occur in any one of the three modules. The proposed voter circuit takes 24 transistors compared to 26 for conventional voter circuit. Results also show 50% percent reduction in falling delay. The proposed voter circuit, using transmission gates takes 14 transistors and power consumption is also significantly reduced.