Design of Low Power MPSoC Architecture using D-R Method

Abstract

In this work, static re-configuration allocates time period for an application as well as dynamic re-configuration termed as processing time re-configuration utilizes a dynamic allocation scheme that reallocates hardware at processing time. The benefits of static reconfiguration are remained, and we can achieve an efficient trade-off between time and space. There are two different memories that use the dynamic re-configurable systems. However, implement run-time reconfiguration onto a single context device, the different full memory should be combined to layers within the configuration memory, and each layer is switched inner and outer layer of the FPGA as needed. Mostly, the benchmark performs unique tasks executed by large number of con-current threads.

Keywords: MPSOC, Low power Design, Wireless communication, Dynamic Allocation.