Download This PaperA Survey on a High Performance Approximate Adder and Two High Performance Approximate Multipliers
IOSR Journal of Business and Management (IOSR - JBM), Journal No. 46879, UGC Serial No. 2953, Impact Factor - 3.52, pp 43 - 50, e-ISSN 2278 - 487X, p-ISSN 2319 - 7668, IOSR.
8 Pages Posted: 26 May 2020 Last revised: 23 Jun 2020
Date Written: June 17, 2018
Abstract
Approximate computing can be performed where exact computing is not required and the applications are resilient to errors (applications will not crush due to approximation). Human perception level is very limited while interpreting an image, an audio or a video. This allows some applications, especially digital signal processing (DSP) applications to produce approximate output instead of exact output. The reason for integrating approximation into the application for reduce the complexity of the circuit which leads reduction in power consumption, delay without degrading the output. In this paper we review one novel approximate adder and two low-power approximate multipliers applicable to high-performance DSP applications. One multiplier for small input produces reductions in delay and power up to 20% and 69%, respectively, when implemented on a 28 nm CMOS process. Another multiplier produces reductions in delay and power up to 9.8% and 10.74%, respectively, with an error rate from 0.2% to 13.76%.
Keywords: Accuracy, Adder, Approximate, High Performance, Multiplier.
JEL Classification: C61
Suggested Citation: Suggested Citation