Shelesh K. Saraswat

Ganeshi Lal Aggarwal University (GLA)

17km Stone, NH-2, Mathura-Delhi Road

P.O. Chaumuhan

Mathura, ID Uttar Pradesh 281 406

India

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Scholarly Papers (1)

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Designing of Power Optimized Down Counter Using Low Voltage CMOS I/O Standard Technology

Proceedings of 3rd International Conference on Internet of Things and Connected Technologies (ICIoTCT), 2018 held at Malaviya National Institute of Technology, Jaipur (India) on March 26-27, 2018
Number of pages: 5 Posted: 09 May 2018
Shelesh K. Saraswat, Tarun Agarwal and Shivanshu Kapoor
Ganeshi Lal Aggarwal University (GLA), Ganeshi Lal Aggarwal University (GLA) and Ganeshi Lal Aggarwal University (GLA)
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