Themozhi G.

AMET University - Department of EEE

India

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A Competent Multiplier Architecture with Reduced Transistor Count for Radix -2 Butterfly Computation of Fast Fourier Transform

TEST Engineering and Management, Page No. 1577 - 1581, March-April 2020
Number of pages: 5 Posted: 14 Apr 2020
SRM Valliammai Engineering College, Valliammai Engineering College - Department of ECE and AMET University - Department of EEE
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Abstract:

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Butterfly Structure, Multiplier, Substrate Biasing, Transistor Count, UrdhyaTiryakbhyam