Design of Cascaded-Integrator-Comb Filter for PSK Modem

Abstract

This paper discusses the implementation of 'Cascaded-Integrator-Comb filter' (CIC) which is a higher order decimation filter for the pulse-shaping of the digital data for PSK modem. They have found a particular niche in digital transmitters and receivers.

The narrow-band extraction from wide band sources requires two basic signal processing procedures: decimation and interpolation. Large rate changes require fast multipliers and very long filters.

This paper presents a Hogenauer devised flexible, multiplier-free Cascaded-Integrator-Comb filter suitable for hardware implementation that can also handle arbitrary and large rate changes. The architecture introduced here includes carry-save implementation of recursive integrator stages, comb stages and a programmable counter for the programmable decimator (21 to 26) which produces selectable power of two output clocks. Carry-save implementation of recursive integrator stages reduces critical path to two full-adder delays between registers. This produces high speed operation, reduces the required chip area, decreases the critical path and reduces the power dissipation.

The project also includes implementation of CIC filter using Verilog and simulation using Maxplus, Xilinx Model and MATLAB. The CIC filter is designed and tested meeting the desired performance goals.