On-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for Fast Fourier Transform Architecture

American Journal of Engineering and Applied Sciences. 3(4):757-764. ISSN 1941-7020 DOI: 10.3844/ajeassp.2010.757.764.

8 Pages Posted: 16 Jul 2012 Last revised: 17 Jul 2012

Yazan Algnabi

affiliation not provided to SSRN

Rozita Teymourzadeh

Neonode Inc

Masuri Othman

affiliation not provided to SSRN

Shabiul Islam

affiliation not provided to SSRN

Mok Vee Hong

affiliation not provided to SSRN

Date Written: July 15, 2010

Abstract

The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This study presents on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly, digit-slicing multiplier-less single constant technique was utilized in the critical path of Radix-2 Decimation In Time (DIT) FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 549.75 MHz with the total equivalent gate count of 31,159 is a marked and significant improvement over Radix 2 FFT butterfly. In comparison with the conventional butterfly architecture, design that can only run at a maximum clock frequency of 198.987 MHz and the conventional multiplier can only run at a maximum clock frequency of 220.160 MHz, the proposed system exhibits better results. The resulting maximum clock frequency increases by about 276.28% for the FFT butterfly and about 277.06% for the multiplier. It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure is an enabler in solving problems that affect communications capability in FFT and possesses huge potentials for future related works and research areas.

Keywords: pipelined digit-slicing multiplier-less, fast fourier transform (FFT), Verilog HDL, Xilinx

JEL Classification: F14, L, O14

Suggested Citation

Algnabi, Yazan and Teymourzadeh, Rozita and Othman, Masuri and Islam, Shabiul and Hong, Mok Vee, On-Chip Implementation of Pipeline Digit-Slicing Multiplier-Less Butterfly for Fast Fourier Transform Architecture (July 15, 2010). American Journal of Engineering and Applied Sciences. 3(4):757-764. ISSN 1941-7020 DOI: 10.3844/ajeassp.2010.757.764. . Available at SSRN: https://ssrn.com/abstract=2107581

Yazan Algnabi

affiliation not provided to SSRN

Rozita Teymourzadeh (Contact Author)

Neonode Inc ( email )

2880 Zanker Rd
Suite 362
San Jose, CA San Jose 95134
United States

HOME PAGE: http://www.rozitateymourzadeh.com/

Masuri Othman

affiliation not provided to SSRN ( email )

Shabiul Islam

affiliation not provided to SSRN

Mok Vee Hong

affiliation not provided to SSRN

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