Techniques for Improving Design Performance of VLSI Circuits and Systems

4 Pages Posted: 14 Apr 2015

See all articles by Kirat Singh

Kirat Singh

Surya World - Department of Electronics and Communication Engineering; CSIR-CSIO

Date Written: July 10, 2014

Abstract

The purpose of this paper is to increase the maximum clock frequency and improve the setup and hold timing by modifying the circuit design. This paper describes the digital gates and memory elements such as latches and registers and can analyze a circuit to find the maximum clock frequency. In this paper we performs to maximize the clock frequency by adding output registers, minimize the setup and hold window by adding input registers, adjust delay measurements when including a delay locked loop (DLL), recalculate the timing of the board-level system after timing modification.

Keywords: Delay, Frequency, Performance, Registers, Clock

JEL Classification: C88

Suggested Citation

Singh, Kirat, Techniques for Improving Design Performance of VLSI Circuits and Systems (July 10, 2014). Available at SSRN: https://ssrn.com/abstract=2594227 or http://dx.doi.org/10.2139/ssrn.2594227

Kirat Singh (Contact Author)

Surya World - Department of Electronics and Communication Engineering ( email )

NH1, Bapror
Tehsil Rajpura, District Patiala
Punjab, 140417
India

CSIR-CSIO ( email )

Chandigarh 160030
India

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