Complexity and Internationalization of Innovation: Why is Chip Design Moving to Asia
International Journal of Innovation Management, Volume 09, Issue 01, March 2005, special issue in honor of Keith Pavitt
23 Pages Posted: 7 Mar 2016 Last revised: 16 Mar 2016
Date Written: March 6, 2005
Among Keith Pavitt’s many contributions to the study of innovation is the proposition that physical proximity is advantageous for innovative activities that involve highly complex technological knowledge (Pavitt, 1999: XI). Cognitive and organizational complexity explain why innovation is an "important case of ‘non-globalisation" (Patel and Pavitt, 1991).
Following this argument, one would expect a highly complex innovative activity like chip design -- a process that creates the greatest value in the electronics industry -- to be spatially immobile, much less prone than manufacturing to geographic relocation. Until quite recently, chip design has indeed remained heavily concentrated in a few centers of excellence, mainly in the US, but also in Europe and Japan. However, fundamental changes have occurred over the last few years in the location of chip design that are signaling a growing geographical mobility. Of particular importance has been a massive dispersion of chip design to leading Asian electronics exporting countries.
The paper explores why chip design is moving to Asia, despite its extraordinary complexity. It shows that Pavitt’s framework can shed new light on the link between complexity and internationalization of innovation. To establish what is really happening, I interviewed 60 companies and 15 research institutions in the US, Taiwan, Korea, China and Malaysia that are involved in electronic design (for integrated circuits as well as systems). In the interviews, I distinguished "pull", "policy" and "push" factors to examine what forces are behind the growing geographic mobility of chip design, and its dispersion to Asia.
"Pull" factors are demand-oriented and supply-oriented forces that attract chip design to particular locations. "Policy" factors are policies and regulations in both home and host countries that affect differences in the cost of conducting innovation across locations. Both factors are roughly identical with the "centrifugal" forces for geographical decentralization that have been identified by research on the internationalization of innovation. I argue that, while "pull" and "policy" forces are important, they may not be sufficient to explain what tilts the balance in favor of decentralization. To reduce this gap in our knowledge, I examine "push" factors, i.e. changes in design methodology ("system-on-chip design", or SoC) and organization ("vertical specialization" within global design networks, or GDNs), and explore the pressures and opportunities that these changes provide for the internationalization of design. Vertical specialization within GDNs implies that stages of chip design are outsourced to specialized suppliers (disintegration of design value chain) and relocated across national boundaries (geographic dispersion). The resultant increase in knowledge mobility explains why chip design that, in Pavitt’s framework is not supposed to move, is moving from the traditional centers to a few new specialized design clusters in Asia.
Part 1 introduces the conceptual framework that underlies the distinction between pull, policy and push factors. Part 2 reviews findings of interviews with main carriers of chip design in Asia that demonstrate substantial progress in the complexity of relocated design stages and capabilities. Part 3 examines the role played by "pull" and "political" factors. "Push" factors are addressed in the rest of the paper. In part 4, I explore how changes in design methodology and organization have pushed vertical specialization within GDNs deeper into the design value chain. Finally, part 5 documents pressures and opportunities that vertical specialization is creating for GDN participants to move chip design to Asia.
Keywords: complexity, internationalization of innovation, globalization, chip design, Asia
JEL Classification: O53, O3, O32, O38
Suggested Citation: Suggested Citation