A Research on Efficient Processor Design Structure with Reduced Memory Gap

International Journal of Advances in Agricultural Sciences and Technology, Vol. 3, Issue 6, p. 60-67, 2016

Posted: 1 Dec 2016

See all articles by Boselin Prabhu

Boselin Prabhu

VSB College of Engineering

E. Gajendran

Sree Dattha Group of Institutions - Department of Computer Science and Engineering

N. Balakumar

Tamil Nadu College of Engineering - Department of Electrical & Electronics Engineering

Date Written: November 24, 2016

Abstract

Vigorous approaches for security are dominant in wireless embedded systems due to the characteristic vulnerability of the fundamental shared medium and the absence of any monitoring structure. To promise security and reliability, most of the current schemes execute periodic reestablishment of authentication authorizations and share secrets among numerous participating nodes. However, the present approaches fail to offer appropriate protection from packet sniffing or eavesdropping attacks. In addition, these methods are energy intensive and fail to scale well in energy-constrained situations. Instead of placing the entire matching pattern on the chip, our solution is the parallel intrusion detection system that works by combining extracting as much of the important filtering information as possible onto a chip and infrequently accessing off chip data to make the matching mechanism suitable for large pattern set. Testing is also introduced to clear the bug which is presented in the network application software. It will improve the coverage of the test, clearly saving in cost and development time. The virus detection and testing processor also protect the multi core systems from Real Time attacks and will provide the formal model–based test for multi core system. With the model a test suite can be extracted from the test case generator and a test program generator will generate test programs automatically. Both generators are assisted with model checking on the formal model. In this paper a detailed research on efficient processor design structure with reduced memory gap has been elaborated.

Keywords: Covert Channel, Embedded Systems, Media Access Control, Physical Layer, Soft Security, Embedded Processor, Memory Gap, Model-Based Test

Suggested Citation

Prabhu, S.R.Boselin and Gajendran, E. and Balakumar, N., A Research on Efficient Processor Design Structure with Reduced Memory Gap (November 24, 2016). International Journal of Advances in Agricultural Sciences and Technology, Vol. 3, Issue 6, p. 60-67, 2016. Available at SSRN: https://ssrn.com/abstract=2875379

S.R.Boselin Prabhu (Contact Author)

VSB College of Engineering ( email )

Coimbatore, Tamil Nadu
India

E. Gajendran

Sree Dattha Group of Institutions - Department of Computer Science and Engineering ( email )

Hyderabad
India

N. Balakumar

Tamil Nadu College of Engineering - Department of Electrical & Electronics Engineering ( email )

Palanisame Ravi Nagar
Tamil, Nadu 641659
India

Register to save articles to
your library

Register

Paper statistics

Abstract Views
33
PlumX Metrics