Design of Low Power Network on Chip Using Data Encoding Techniques
International Journal of Recent Advances in Multidisciplinary Research Vol. 04, Issue 04, Pp.246 8 - 2475, April, 2017
8 Pages Posted: 16 Aug 2017
Date Written: April 2017
An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC makers at all of this into one chip. A contrast of Network On Chip’s (NoC’s) structure makes a fitting replacement for System On Chip (SoC) design in designs incorporating large number of processing cores. In NoC the overall power dissipation is due to the interconnection system. The interconnects have become main element in dynamic power dissipation in a NoC design. NoC improves the scalability of SoC and the power efficient of complex SoC compared to other designs. The wires in the links of the NoC are shared by many signals. The project concept depends on the traffic flow in the chip. The idea presented in this project exploits the wormhole switching techniques and works on an end to end basis. That is flits are encoded by the Network Interface (NI) before they are injected in the network and are decoded by the destination NI. In such a way as to minimize both switching activity and the coupling switching activity which represent the main factors of power dissipation. The proposed schemes are general and transparent with respect to the underlying NoC fabrication. The data encoding technique in which number of switching transitions in data word is brought down to reduce the power dissipation. To verify the efficiency of the proposed technique, encoder structure was designed by using VerilogHDL. As result, we save the power on NoC links more than 50%.
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