Detection of Stuck Open and Short Fault in SRAM Based System
4 Pages Posted: 27 Feb 2018
Date Written: November 15, 2017
A novel scan-based Built-In Self-Test (BIST) architecture is designed with Low-Power (LP) for weighted pseudorandom test pattern generation (WPTPG) and reseeding, which is easy for the pseudorandom testing and deterministic BIST. The pseudorandom testing stage is designed by disabling a section of scan chains and in the deterministic BIST stage, the design-for-testability architecture is reorganize slightly while the linear-feedback shift register is kept short. The proposed technique of a BIST design for fault detection and fault diagnosis of Static-RAM (SRAM) based Field Programmable Gate Array (FPGAs) can detect the interconnect resources in the Configurable Logic Blocks (CLBs). The test pattern generator and output response analyzer are configured by CLBs in FPGAs. The testing procedure undergoes three major test blocks. They are Test Pattern Generator (TPG), Output Response Analyzer (ORA) and Block Under Test (BUT) in each test block. The stuck open and short faults are detected using SRAM based FPGA are observed in this paper.
Keywords: low power; SRAM based FPGA; BIST; CLBs
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