Implement and Analysis of a 1-Bit Ternary SRAM Cell Using Tanner Tools
Proceedings of 3rd International Conference on Internet of Things and Connected Technologies (ICIoTCT), 2018 held at Malaviya National Institute of Technology, Jaipur (India) on March 26-27, 2018
8 Pages Posted: 3 May 2018
Date Written: April 21, 2018
Binary logic dominates present day digital systems. Today the complexity of binary systems is on the rise because of increasing number of gates per chip and more complex circuit schematics. To upkeep Moore’s law, gate count per chip is exponentially increasing leading to more complex circuits and greater number of interconnections, which cover almost 70 percent of chip area. More gates also increase power consumption and dissipation per chip. Under such circumstances, multivalued logic approach provides several advantages over existing binary digital system and research has concluded ternary system to be the most efficient in terms of logic computations. Using existing mathematical models of basic Ternary gates, the schematics is obtained for the same. In this paper the focus is on implementation of this Ternary inverter and application of the ternary inverter to design a 1-bit ternary Static Random-Access Memory (SRAM) cell having low power consumption on the basis of Simple, Positive and Negative Ternary Inverter.
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