Designing of Power Optimized Down Counter Using Low Voltage CMOS I/O Standard Technology
Proceedings of 3rd International Conference on Internet of Things and Connected Technologies (ICIoTCT), 2018 held at Malaviya National Institute of Technology, Jaipur (India) on March 26-27, 2018
5 Pages Posted: 9 May 2018
Date Written: April 29, 2018
The designing of a 4-bit Down Counter has a simple but robust specification, but it allows N-number of energy and power efficient implementations. The designs are basically analysed on the basis of area, response time and power consumption. In this paper, we have focused on the use of power efficient LVCMOS I/O standard for the VLSI design of Down- Counter. We have validated our circuit at 4 different I/O Standards, namely – LVCMOS 15, LVCMOS 18, LVCMOS 25; and for 3 technologically advanced families – Artix 7 (28 nm), Virtex 6 (40 nm) and Spartan 6 (45 nm).There is a 7.136% and 25.085% reduction, in power consumption, when LVCMOS 15 is used instead of LVCMOS 18 and LVCMOS 25 respectively; and a 84.18% and 34.88% reduction when ARTIX-7 is used in place of VIRTEX-6 and SPARTAN-6 respectively. It was also observed that at 25°C, there is a reduction of 20.69 %, 30.79%, 39.96% and 47.10% in power utilization when the circuit is operated at 1GHz instead of 2GHz, 3GHz, 4GHz and 5GHz respectively at 50% Duty Cycle.
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