Dual Edge-Triggered D-Type Flip-Flop with Low Power Consumption

International Journal of Computer Science & Information Technology (IJCSIT) Vol 10, No 5, October 2018

12 Pages Posted: 27 Nov 2018

See all articles by Chien-Cheng Yu

Chien-Cheng Yu

National Chung Hsing University

Ching-Chith Tsai

National Chung Hsing University

Date Written: November 5, 2018

Abstract

In this paper, a novel low-power dual edge-triggered (DET) D-type flip-flop is proposed. This design achieves dual edge-triggered with two parallel data paths work in opposite phases of the clock single. Among them, a latch circuit structure employs differential input data signals which deposits very little capacitance on the clock line is accomplished. For fair comparison, four previously reported DET flipflops along with the proposed DETFF (DET flip-flop) are compared in terms of power consumption and power-delay product (PDP), under different data activities and different data rates. Several HSPICE simulation results show that the proposed DETFF is superior in power reduction at different parameters as compared to the existing DETFFs. Hence, the proposed DETFF is well suited for low power applications.

Keywords: Single Edge-Triggered (SET), Dual Edge-Triggered (DET), Flip-Flop, Power Consumption, Power-Delay Product (PDP)

Suggested Citation

Yu, Chien-Cheng and Tsai, Ching-Chith, Dual Edge-Triggered D-Type Flip-Flop with Low Power Consumption (November 5, 2018). International Journal of Computer Science & Information Technology (IJCSIT) Vol 10, No 5, October 2018. Available at SSRN: https://ssrn.com/abstract=3278480

Chien-Cheng Yu (Contact Author)

National Chung Hsing University

402, No. 250 Kuo Kuang Road, Taiwan
Taichung, Taiwan
China

Ching-Chith Tsai

National Chung Hsing University

402, No. 250 Kuo Kuang Road, Taiwan
Taichung, Taiwan
China

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