Performance Evaluation of Low Power Carry Save Adder for VLSI Applications

International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018

8 Pages Posted: 13 Dec 2018

Date Written: June 21, 2018

Abstract

This report examines the subject of sub threshold leakage on carry save adder. When the gate to source voltage reduces to the threshold voltage at that place is yet some amount of current flow in the circuit and that is undesired. As the process technology advancing much rapidly the threshold voltage of MOS devices reduces very drastically, and it must be applied in lower power devices since it contributes to low amount of leakage current which confine increases the power consumption of the devices. Adders are the basic building blocks for any digital circuit design and used in almost all arithmetic’s. The CSA proves efficient adders due to its quick and precise computations. Hence this paper performs sub threshold analysis on CSA and the scrutinize results that the total average power is around 4.93µW, the propagation delay for complete operation is 16.3ns and since this design uses GDI cell so there is a reduction in area with 37%.

Keywords: Sub threshold Leakage; Gate Diffusion Input (GDI); Carry Save Adder (CSA); Leakage current; Transistor Modeling;

Suggested Citation

Tripathi, Divya and Wairya, Subodh, Performance Evaluation of Low Power Carry Save Adder for VLSI Applications (June 21, 2018). International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018, Available at SSRN: https://ssrn.com/abstract=3288356

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