Vlsi Implementation of Area Efficient 2-Parallel Fir Digital Filter

International Journal of VLSI design & Communication Systems (VLSICS) Vol.7, No.5/6, December 2016

8 Pages Posted: 13 Jun 2019

See all articles by L Kholee Phimu

L Kholee Phimu

affiliation not provided to SSRN

Manoj Kumar

Department of Mathematics, Motilal Nehru National Instituteof Technology,Allahabad,Prayagraj(UP)-211004,,India

Date Written: December 2016

Abstract

This paper aims to implement an area efficient 2-parallel FIR digital filter. Xilinx 14.2 is used for synthesis and simulation. Parallel filters are designed by using VHDL. Comparison among primary 2–parallel FIR digital filter and area efficient 2-parallel FIR digital filter has been done. Since adders are less weight in term of silicon area, compare to multipliers. Therefore multipliers are replaced with adders for reducing area and speed of the filter. 2-parallel FIR filter is used in digital signal processing (DSP) application.

Keywords: Finite impulse response (FIR), Booth multiplier, Carry-look-ahead adder (CLA), Digital Signal Processing (DSP), Parallel FIR, Very Large Scale Integration (VLSI)

Suggested Citation

Phimu, L Kholee and Kumar, Manoj, Vlsi Implementation of Area Efficient 2-Parallel Fir Digital Filter (December 2016). International Journal of VLSI design & Communication Systems (VLSICS) Vol.7, No.5/6, December 2016. Available at SSRN: https://ssrn.com/abstract=3396461 or http://dx.doi.org/10.2139/ssrn.3396461

L Kholee Phimu (Contact Author)

affiliation not provided to SSRN

Manoj Kumar

Department of Mathematics, Motilal Nehru National Instituteof Technology,Allahabad,Prayagraj(UP)-211004,,India ( email )

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