Design of a Low Power and High Speed Wallace Tree Encoder for Flash ADC

6 Pages Posted: 9 Jan 2020

See all articles by Sarfraz Hussain

Sarfraz Hussain

North Eastern Regional Institute of Science and Technology (NERIST)

Rajesh Kumar

North Eastern Regional Institute of Science and Technology (NERIST)

Date Written: January 9, 2020

Abstract

An improved design of Wallace tree encoder is presented in this paper. Wallace tree encodes a thermometer code into binary code in a Flash ADC. It has the advantage of correcting bubble errors without the need of an extra bubble error correcting (BEC) block. It consists of full adder circuits and adds the number of 1’s generated through the comparator output in a Flash ADC. The new Wallace tree encoder is compared with the previously designed traditional Wallace tree encoder in 45nm technology. The results show that new design is efficient than the previous design. The proposed encoder dissipates 9.61μW power and has a delay of 29.5ps. The PDP and EDP is calculated to be 0.28 fJ and 0.83x10-26 Js.

Keywords: Encoder, Flash ADC, Full Adder, High Speed, Low Power, Wallace Tree Encoder

Suggested Citation

Hussain, Sarfraz and Kumar, Rajesh, Design of a Low Power and High Speed Wallace Tree Encoder for Flash ADC (January 9, 2020). Proceedings of the 5th International Conference on Computers & Management Skills (ICCM 2019) | North Eastern Regional Institute of Science & Technology (NERIST), Nirjuli, Arunachal Pradesh, India, Available at SSRN: https://ssrn.com/abstract=3516639 or http://dx.doi.org/10.2139/ssrn.3516639

Sarfraz Hussain (Contact Author)

North Eastern Regional Institute of Science and Technology (NERIST) ( email )

Itanagar

Rajesh Kumar

North Eastern Regional Institute of Science and Technology (NERIST) ( email )

Itanagar

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