FPGA Implementation of Priority Arbiter Based Router Design for NOC Systems

International Journal of Advanced Research in Engineering and Technology, 10(2), 2019, pp 509-516

8 Pages Posted: 11 Mar 2020

See all articles by Nirmala M

Nirmala M

Department of ECE, Bangalore Institute of Technology, VV Puram Bengaluru, India

Shylaja V

Assistant Professor, Department of ECE, Bangalore Institute of Technology, VV Puram Bengaluru, India

Date Written: 2019

Abstract

An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh topology-based NOC architecture are designed. The Priority –Arbiter based Router design includes Input registers, Priority arbiter, and XY- Routing algorithm. The Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized and implemented using Xilinx ISE Tool and simulated using Modelsim 6.5f. The implementation is done by Artix-7 FPGA device, and the physically debugging of the NOC 2X2 Router design is verified using Chipscope pro tool. The performance results are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum operating frequency. The comparison of the Priority-Arbiter based Router is made concerning previous similar architecture with improvements.

Keywords: NoC, SoC, Router, FPGA

Suggested Citation

M, Nirmala and V, Shylaja, FPGA Implementation of Priority Arbiter Based Router Design for NOC Systems (2019). International Journal of Advanced Research in Engineering and Technology, 10(2), 2019, pp 509-516. Available at SSRN: https://ssrn.com/abstract=3536247

Nirmala M (Contact Author)

Department of ECE, Bangalore Institute of Technology, VV Puram Bengaluru, India ( email )

Bengaluru
India

Shylaja V

Assistant Professor, Department of ECE, Bangalore Institute of Technology, VV Puram Bengaluru, India ( email )

Bengaluru
India

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