A Competent Multiplier Architecture with Reduced Transistor Count for Radix -2 Butterfly Computation of Fast Fourier Transform

TEST Engineering and Management, Page No. 1577 - 1581, March-April 2020

5 Pages Posted: 14 Apr 2020

See all articles by Saravanakumar Chandrasekaran

Saravanakumar Chandrasekaran

SRM Valliammai Engineering College

Usha Bhanu

Valliammai Engineering College - Department of ECE

Themozhi G.

AMET University - Department of EEE

Date Written: March 18, 2020

Abstract

Multiplication is the elementary process for computing the butterfly in Fast Fourier Transform. A formal multiplication task requires an extensively additional hardware means and processing time in multiplication operation to a certain degree more than in addition and subtraction. In this work, architecture for multiplier is proposed which requires less space and works faster comparatively with other basic multiplier structures. The “UrdhvaTiryakbhyam” scheme offered by Vedic Mathematics is utilized to speed up the multiplication process. In addition, the reduction in transistor count is achieved by substrate biasing. Further the architecture is simulated in ORCAD software to analyse the area requirements of the Butterfly structure for computing Fast Fourier Transforms. The simulated results show that there is considerable reduction in transistor count and operating speed which makes the proposed multiplier a competent one with the standard multiplier architecture.

Keywords: Butterfly Structure, Multiplier, Substrate Biasing, Transistor Count, UrdhyaTiryakbhyam

JEL Classification: VLSI, Signal Processing

Suggested Citation

Chandrasekaran, Saravanakumar and Bhanu, Usha and G., Themozhi, A Competent Multiplier Architecture with Reduced Transistor Count for Radix -2 Butterfly Computation of Fast Fourier Transform (March 18, 2020). TEST Engineering and Management, Page No. 1577 - 1581, March-April 2020, Available at SSRN: https://ssrn.com/abstract=3556542 or http://dx.doi.org/10.2139/ssrn.3556542

Saravanakumar Chandrasekaran (Contact Author)

SRM Valliammai Engineering College ( email )

Department of ECE
SRM Nagar, Kattankulathur - 603 203
Chennai, TN Tamilnadu 603203
India

Usha Bhanu

Valliammai Engineering College - Department of ECE ( email )

India

Themozhi G.

AMET University - Department of EEE ( email )

India

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