Design of a Four-stage Pipelined Reduced Instruction Set Computing Microprocessor

Posted: 16 Jul 2020

See all articles by Jinfeng LI

Jinfeng LI

Department of Electrical and Electronic Engineering, Imperial College London

Date Written: June 1, 2020

Abstract

This work presents the design of a reduced instruction set computing (RISC) microprocessor in a four-stage pipeline architecture. The nuts and bolts of each block including timing diagrams are elaborated. To be more specific, a hardware solution to pipeline hazards is proposed and verified, i.e. provided the current result of the arithmetic logic unit (ALU) is employed by the next instruction, the FOWARDING_EN goes high and commands the ALU to select the forwarded result as the updated input, rather than the stale value read from the random-access memory (RAM), thus obviating the need to wait for another two cycles until the expected data has been written back. For the design with data forwarding, two limitations were discovered and tackled successfully by a software solution. Active-HDL was employed to verify the design by simulating a case study, with the code presented in the Appendix.

Keywords: active-HDL; data forwarding; microprocessor; pipeline hazard; RISC.

Suggested Citation

LI, Jinfeng, Design of a Four-stage Pipelined Reduced Instruction Set Computing Microprocessor (June 1, 2020). Available at SSRN: https://ssrn.com/abstract=3615850 or http://dx.doi.org/10.2139/ssrn.3615850

Jinfeng LI (Contact Author)

Department of Electrical and Electronic Engineering, Imperial College London ( email )

South Kensington Campus
Exhibition Road
London, Greater London SW7 2AZ
United Kingdom

HOME PAGE: http://www.imperial.ac.uk/people/jinfeng.li

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