Efficient Verification and Synthesis Using Design Commonalities
10 Pages Posted: 17 Nov 2020
Date Written: 1998
In this paper we solve the problem of identifying a "matching" between two logic circuits or "networks". A matching is a functions that maps each gate or "node" in the new circuit into one in the old circuit (if a matching does not exist it maps it to null). We present both an exact and a heuristic way to solve the maximal matching problem. The matching problem does not require any input correspondences. The purpose is to identify structurally identical regions in the networks, and exploit the commonality between them for more efficient verification and synthesis.
Synthesis and verification tools that recognize commonalities both between two versions of the same design, as well within a single design, may be able to outperform their counterparts that do not utilize these commonalities. This work is concerned with detecting structural "matchings" that may be re-utilized.
Keywords: incremental algorithms, iterative design, computer aided design, logic network mapping
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