Minimal Logic Re-synthesis

17 Pages Posted: 17 Nov 2020

See all articles by Gitanjali Swamy

Gitanjali Swamy

PCRI, Harvard Business School; IoTask; University of California, Berkeley; Auto-ID Center, MIT

Sriram Rajamani

affiliation not provided to SSRN

Chris Lennard

affiliation not provided to SSRN

Robert K. Brayton

affiliation not provided to SSRN

Date Written: 1997

Abstract

Most problems in logic synthesis are computationally hard and are solved using heuristics. This often makes algorithms un-stable; if the input is changed slightly, the new result of synthesis can be significantly different. A designer can spend much effort hand-optimizing a circuit, so it is desirable to retain as much of this human insight as possible. This motivates the need for incremental synthesis. We propose a re-synthesis algorithm, which allows the designer to designate non-resynthesizable portions of a circuit. We define the concept of minimal change caused by re synthesis, i.e. given a functional change to the circuit, we examine the minimal change to implement this change. For the evaluation of a region for re-synthesis we present techniques for evaluating the “sensitivity” or gain possible with resynthesis of a set of nodes. We conclude with experimental results and future directions.

Keywords: incremental algorithms, iterative design, computer aided design, logic network mapping

Suggested Citation

Swamy, Gitanjali and Rajamani, Sriram and Lennard, Chris and Brayton, Robert K., Minimal Logic Re-synthesis (1997). Available at SSRN: https://ssrn.com/abstract=3702091 or http://dx.doi.org/10.2139/ssrn.3702091

Gitanjali Swamy (Contact Author)

PCRI, Harvard Business School ( email )

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IoTask ( email )

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University of California, Berkeley ( email )

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Auto-ID Center, MIT ( email )

Sriram Rajamani

affiliation not provided to SSRN

Chris Lennard

affiliation not provided to SSRN

Robert K. Brayton

affiliation not provided to SSRN

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