Error Correction LDPC Encoder with Bit-Flipping Decoder
7 Pages Posted: 25 Nov 2020
Date Written: November 20, 2020
The communication method conveys information from the transmitter to the receiver over an intermediate medium. The competence of received information is determined by medium and clatter. There is a great need for robust error correction techniques with ever accumulative usage of wireless expedients such as portable electronic items and broadband modems. Wireless communication schemes depend on advanced error rectification techniques for their suitable functioning. Hence transferring and getting information with less or without error, while utilizing the accessible bandwidth is a foremost proposal, project necessities for present digital wireless communication systems comprising of high throughput, low power consumption, and less area. In this article, the functional analysis is performed for error control coding technique i.e., Low-Density-Parity-Check (LDPC) coding in terms of device utilization and power. The functional verification and the simulation are performed using Verilog HDL. Error correction techniques such as Linear block codes, RS codes, Convolutional codes are employed to implement forward error correction but as the constraint length increases the design of decoders becomes more complex. LDPC is a type of block code that is capable of correcting random errors. They are popular because of their eminent detection and correction capabilities. LDPC encoding technique provides high throughput and aims to improve BER when compared to conventional techniques. The decoding of LDPC codeword employs the Message Passing Algorithm, where each bit in a codeword is allocated to special nodes. The performance of these codes is hence better and easily attains Shannon’s limit than the previously used codes. Synthesis for the technique is performed and utilization reports are derived from the synthesis in Vivado.
Keywords: Bit flipping algorithm, Low-Density-Parity-Check (LDPC), Parity Check Matrix
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