Implementation and Comparative Analysis of Low Power Multiplexers Using Dynamic Logic Styles

9 Pages Posted: 25 Nov 2020

See all articles by Rajendran V.G

Rajendran V.G

Shanmugha Arts, Science, Technology & Research Academy (SASTRA) - SASTRA Deemed University

Dr.Jayalalitha S.

Shanmugha Arts, Science, Technology & Research Academy (SASTRA) - SASTRA Deemed University

Thalaimalaichamy M.

Shanmugha Arts, Science, Technology & Research Academy (SASTRA) - SASTRA Deemed University

Nilavazhahan K.S

SASTRA Deemed University

Date Written: November 21, 2020

Abstract

This paper presents the implementation and comparative analysis of low power multiplexers using dynamic logic styles. A multiplexer is a digital circuit with 2N input lines with N selection lines and gives a single output. Dynamic logic styles were used in conventional CMOS for optimizing power, area, and delay, etc. Different types of dynamic logic styles such as complementary CMOS, pseudo NMOS, domino differential cascade voltage switch logic, low power feed through logic, and clocked CMOS logic were used for the implementation of a multiplexer. In this present work, the implementation of 2:1 multiplexer using different dynamic logic styles with various technologies (120nm, 90nm, 70nm) and the performance parameters such as power consumption and delay were compared and analyzed. The clocked CMOS was found efficient in low power consumption and fast switching speed. Among the different logic styles, Domino, clocked and low power feed through logic produces efficient in delay and power consumption. The implementation and simulation of low power multiplexers were carried out by using DSCH 2.6F microwind tool.

Keywords: Multiplexer, dynamic logic styles, CMOS, NMOS, domino logic, power consumption.

Suggested Citation

V.G, Rajendran and S., Dr.Jayalalitha and M., Thalaimalaichamy and K.S, Nilavazhahan, Implementation and Comparative Analysis of Low Power Multiplexers Using Dynamic Logic Styles (November 21, 2020). Proceedings of the 2nd International Conference on IoT, Social, Mobile, Analytics & Cloud in Computational Vision & Bio-Engineering (ISMAC-CVB 2020), Available at SSRN: https://ssrn.com/abstract=3734783 or http://dx.doi.org/10.2139/ssrn.3734783

Rajendran V.G (Contact Author)

Shanmugha Arts, Science, Technology & Research Academy (SASTRA) - SASTRA Deemed University ( email )

School of Computing
SASTRA Deemed University
Tirumalaisamudram, Thanjavur, TN Tamil Nadu 613401
India

Dr.Jayalalitha S.

Shanmugha Arts, Science, Technology & Research Academy (SASTRA) - SASTRA Deemed University ( email )

School of Computing
SASTRA Deemed University
Tirumalaisamudram, Thanjavur, TN Tamil Nadu 613401
India

Thalaimalaichamy M.

Shanmugha Arts, Science, Technology & Research Academy (SASTRA) - SASTRA Deemed University ( email )

School of Computing
SASTRA Deemed University
Tirumalaisamudram, Thanjavur, TN Tamil Nadu 613401
India

Nilavazhahan K.S

SASTRA Deemed University ( email )

India

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