High Speed and Area Efficient 2D DWT Processor Based Image Compression

Signal & Image Processing : An International Journal(SIPIJ) Vol.1, No.2, December 2010

10 Pages Posted: 23 Jul 2021

See all articles by Sugreev Kaur

Sugreev Kaur

National Institute of Technical Teachers Training & Research

Rajesh Mehra

National Institute of Technical Teachers Training & Research

Date Written: 2010

Abstract

This paper presents a high speed and area efficient DWT processor based design for Image Compression applications. In this proposed design, pipelined partially serial architecture has been used to enhance the speed along with optimal utilization and resources available on target FPGA. The proposed model has been designed and simulated using Simulink and System Generator blocks, synthesized with Xilinx Synthesis tool (XST) and implemented on Spartan 2 and 3 based XC2S100-5tq144 and XC3S500E-4fg320 target device. The results show that proposed design can operate at maximum frequency 231 MHz in case of Spartan 3 by consuming power of 117mW at 28 degree/c junction temperature. The result comparison has shown an improvement of 15% in speed.

Keywords: DCT, DFT, DWT, JPEG, FPGA

JEL Classification: Signal & Image Processing

Suggested Citation

Kaur, Sugreev and Mehra, Rajesh, High Speed and Area Efficient 2D DWT Processor Based Image Compression (2010). Signal & Image Processing : An International Journal(SIPIJ) Vol.1, No.2, December 2010, Available at SSRN: https://ssrn.com/abstract=3877222

Sugreev Kaur (Contact Author)

National Institute of Technical Teachers Training & Research ( email )

India

Rajesh Mehra

National Institute of Technical Teachers Training & Research ( email )

India

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