Design of Low Power Phase Locked Loop (PLL) Using 45NM VLSI Technology

International journal of VLSI design & Communication Systems ( VLSICS ), Vol.1, No.2, June 2010

11 Pages Posted: 11 Aug 2021

See all articles by Ujwala A. Belorkar

Ujwala A. Belorkar

Shree Hanuman Vyayam Prasark Mandal - Department of Electronics & Telecommunication

S. A. Ladhake

Sipna College Of Engineering And Technology

Date Written: 2010

Abstract

Power has become one of the most important paradigms of design convergence for multi gigahertz communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The core of a microprocessor, which includes the largest power density on the microprocessor. In an effort to reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of dynamic and static power consumption. Lowering the supply voltage, however, also reduces the performance of the circuit, which is usually unacceptable. One way to overcome this limitation, available in some application domains, is to replicate the circuit block whose supply voltage is being reduced in order to maintain the same throughput .This paper introduces a design aspects for low power phase locked loop using VLSI technology. This phase locked loop is designed using latest 45nm process technology parameters, which in turn offers high speed performance at low power. The main novelty related to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnect dielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD, practical experience in layout design

Keywords: Phase locked loop (PLL), voltage-controlled oscillator (VCO), 45nm technology, VLSI technology, low power.

JEL Classification: VLSI design & Communication Systems

Suggested Citation

Belorkar, Ujwala A. and Ladhake, S. A., Design of Low Power Phase Locked Loop (PLL) Using 45NM VLSI Technology (2010). International journal of VLSI design & Communication Systems ( VLSICS ), Vol.1, No.2, June 2010, Available at SSRN: https://ssrn.com/abstract=3887417

Ujwala A. Belorkar (Contact Author)

Shree Hanuman Vyayam Prasark Mandal - Department of Electronics & Telecommunication ( email )

India

S. A. Ladhake

Sipna College Of Engineering And Technology ( email )

United States

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