Performance Modelling and Optimal Stage Assignment for Multistage P4 Switches

Abstract

P4 programmable switches typically consist of multiple computation stages, each capable of independently executing flow rules to achieve the desired network function (NF). A network function chain (NFC) can be implemented to provide a network service by concatenating a set of NFs. This paper focuses on studying the stage-to-NF assignment problem in multistage P4 switches. We propose a greedy-based stage assignment algorithm that has been proven to optimally solve such resource allocation problems. The algorithm's key feature is its ability to address load imbalances among the NFs by considering both the packet arrival and service rates of the NFs. During each iteration of the algorithm's execution, a set of stage assignments needs to be evaluated. To efficiently determine the average packet delay for each assignment, we have developed a queuing model and derive an analytical solution. The analytical results are verified through simulation, and the gap between them is found to be negligible. Additionally, the simulation results demonstrate the algorithm's superiority in handling load imbalances among NFs. The algorithm efficiently assigns stages such that, for a set of NFCs with a constant total input rate, altering the distribution of arrival rates among the NFCs results in similar average delays. The experimental instances indicate that the variation in delay remains within 8% after altering the arrival rate distribution among the NFCs. Furthermore, we implemented a benchmark named “Equal Stage Assignment” in which each NF is assigned an equal number of stages. Compared to the Equal Stage Assignment algorithm, the proposed stage assignment algorithm can reduce the average delay by more than 20%, particularly in cases where the loads between NFs are imbalanced.

Keywords: Network function to stage assignment, P4 queueing model, Average delay minimization