An Adaptive GM Cell Compensation Technique for Fast Transient and High Efficiency Ldo Without On/Off-Chip Capacitor

Abstract

This paper introduces a high current efficiency capacitor-less low dropout regulator (LDO) designed for low-power applications, focusing on fast transient response and high power supply rejection (PSR) at high-frequency. The proposed adaptive $G_m$ cell compensation (AGCC) technique replaces the traditional capacitor compensation, ensuring stability across the full load range while preserving bandwidth. The design resolves the trade-off between bandwidth and power consumption by integrating adaptive biasing and substrate driving techniques, achieving fast transient response and high PSR at high-frequency. The LDO operates with input voltages from 1.0 V to 1.2 V and an output voltage of 0.8 V. It maintains a quiescent current of 223 nA at 27 $^\circ C$ with no load. The current efficiency exceeds 88.5 $\%$ and peaks at 99 $\%$ for loads between 10 $\mu$A and 20 mA. The worst-case post simulation in a 40 nm CMOS process with an area of 0.001925 mm$^2$ shows the PSR is below -17 dB and -37 dB at 1 MHz for 1 mA and 20 mA loads, with a figure of merit of 0.027 fs.

Keywords: capacitor-less LDO, low-power, fast transient response, high power supply rejection (PSR), adaptive $G_m$ cell compensation (AGCC)