A High Accuracy Sample and Hold Circuit with Reduced Non-Linearity Errors for SAR ADC in 45nm CMOS process

Abstract

This manuscript presents a novel Sample and Hold circuit with reduced charge injection, clock feed-through and coupling effects. Designing of a clock booster is an important attribute in the proposed bootstrap circuit. The Non-ideal effects of switches are Charge injection, Clock feed through and Coupling effect. These Non-ideal effects have been reduced by using a dummy switch and transmission gate methods. The Coupling effect has been greatly reduced and improved the accuracy of the Sample and Hold circuit by using full differential architecture. This Sample and Hold circuit is designed in the 45nm CMOS process which operates at 1.1V of supply voltage. The experimental outcomes show that the Sample and Hold circuit reaches the Effective Number of Bits (ENOB) greater than 12 bits, Spurious Free Dynamic Range (SFDR) of 62 dB and Signal to Noise Ratio (SNR) of 64.7 dB for a 13KHz input signal frequency through 200KS/s sampling rate which consumes 7.18 of power. The total harmonic distortion of the proposed Sample and Hold circuit is 0.248%.