Load-Driven Inductive Peaking Design for Broad Band Continuous-Time Linear Equalizer

Abstract

This article presents modeling and analysis of several wideband current-mode logic (CML) continuous-time linear equalizers (CTLEs), including series peaking, shunt peaking, T-coil peaking, and bridged-shunt T-coil peaking architectures. Theoretical analysis reveal the peaking gain-bandwidth product (PGBW) of each structure. The series peaking configuration achieves the highest PGBW when the parasitic capacitance CD is comparable to the load capacitance CL, corresponding to larger input transistor sizes. In contrast, the bridged-shunt T-coil peaking structure delivers superior PGBW performance when CD is significantly smaller than CL. Based on these modeling insights, an analog front-end (AFE) circuit is designed in 28-nm CMOS technology for a 112-Gb/s PAM-4 medium-reach (MR) receiver (RXs), targeting scenarios where CD is relatively small. The proposed AFE adopts a bridged-shunt T-coil peaking structure to extend the bandwidth. Post-layout simulations demonstrate that the proposed AFE achieves a boost gain of up to 21.5-dB dissipating 43.8 mW at a 0.9-V supply, achieving larger than 28-GHz bandwidth within the area of 0.06 mm².

Keywords: Bandwidth expansion technology, Bridged-Shunt T-coil peaking, peaking gain bandwidth product (PGBW), analog front end (AFE), Continuous-Time Linear Equalizer (CTLE).