1 Anam-dong 5 ka
Seoul, 136-701
Korea, Republic of (South Korea)
Korea University
Source/drain contact, contact resistance, metal/interlayer/semiconductor structure, Fermi-level unpinning, reduced graphene oxide
oxide semiconductor, contact resistivity, Schottky barrier height, Fermi-level pinning, MIS contact
Graphene, MoTe2, Polarity control, Metal-interlayer-semiconductor, Source/drain contact
negative differential resistance, peak voltage, peak-to-valley current ratio, ternary inverter, multi-valued logic